The default host for the PAK is the Parallax Basic Stamp. However, the PAK protocol is very simple and any processor can take advantage of it. (Note that the PAK-V and PAK-VI use simple RS232 protocol; however, the other PAKs use the protocol described in this document.)
In general, interfacing a PAK to a new host will require 4 routines:
1. A routine to reset the PAK
2. A routine to send a byte to the PAK
3. A routine to receive a byte from the PAK
4. A routine to wait for a ready condition (may be an optional part of the receive code)
You can find code already written for the SX, PIC, AVR (assembly or BASCOM), BX24, and 68HC11 (assembly or SBasic).
If you want to roll your own, here's the basic timing of the protocol:
The host connects to the PAK with a clock line (always an output) and either 1 or 2 data lines. If your processor can't support a line that is sometimes and input and sometimes an output, you'll need to use 2 data lines. If you can switch a pin between input and output you can use a single pin and connect it to both the SIN and SOUT pins on the PAK. In any event, SOUT needs a pull up resistor as shown in the manual.
To send a byte to the PAK, you set the most significant bit and pulse the clock from low to high. The data must be valid on the rising edge of the clock line. Then return the clock low and repeat until all bits are complete.
If the data line goes from low to high while the clock is high then the chip will reset its communications system. This is a good idea when your program first starts as it puts the communications system in a known state. Here is a scope trace of a typical reset (note x10 probes are in use, so the signals are about 5V, not .5V as the legend indicates). The top green trace is the clock and the lower yellow trace is the data line:
Reception is similar. The host samples the data line and then pulses the clock. The first sample is the most significant bit and you sample until you've read all 8 bits. Certain PAKs use the initial bit to signify readiness. These operations are set up to always output an initial 0 bit. So if the host sees the data line is high, it should not clock the PAK in this case. Some commands don't take an appreciable amount of time to execute and therefore they don't follow this convention. For example, a PAK I multiply command returns a status which always starts with a 0 bit. However, the RIO command (which reads an input port) does not always start with a 0. This is not a problem since RIO takes practically no time to execute compared to a multiply.
For PAKs with a 10MHz resonator, the clock frequency should not exceed 50kHz. For 20MHz and 50MHz PAKs you should keep the clock below 100kHz. Slower speeds are fine but don't maintain the clock high for more than 2 seconds or some PAKs will reset (this can be a problem if you are trying to single step code that uses the PAK -- make sure the clock line pulses).
For reference, the Basic Stamp II uses a 16kHz frequency and the Stamp IISX uses 42kHz. Keep in mind that these frequencies are just the I/O time. You also need to allow time for the PAK to perform its task (PAKs that take significant time to process commands will have a mechanism for informing you when it is ready to send data).
Here is a scope shot of a Motorola 68HC11 sending a command $8 to a PAK-I. Again, the clock is on top in green and the data is below in yellow. Notice that the short pulses on the data line are ignored because the clock is low at those times. Only the wide pulse under the fifth clock pulse is a legitimate 1.
This is the COMMCHK command, and a PAK-I will respond with a $22, like this:
Again, the slender pulses on the data line are not true 1's because they are in between clock cycles.
The most common interface has the SIN and SOUT pins tied together with a pull up resistor. This works because SOUT is effectively open collector (or open drain if you prefer). However, it is possible to connect SIN and SOUT to separate pins if the host does not support a single pin that is both input and output. In this case, it is important that SIN remain HIGH any time that the PAK is transmitting data to the host. If SIN is left low, the PAK may interpret this as a reset condition.
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